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1/21 L6910 L6910a july 2003 feature n operating supply voltage from 5v to 12v buses n up to 1.3a gate current capability n adjustable output voltage n n-inverting e/a input available n 0.9v 1.5% voltage reference n voltage mode pwm control n very fast load transient response n 0% to 100% duty cycle n power good output n overvoltage protection n hiccup overcurrent protection n 200khz internal oscillator n oscillator externally adjustable from 50khz to 1mhz n soft start and inhibit n packages: so-16 & htssop16 applications n supply for memories and termi- nations n computer add-on cards n low voltage distributed dc-dc n mag-amp replacement description the device is a pwm controller for high performance dc-dc conversion from 3.3v, 5v and 12v buses. the output voltage is adjustable down to 0.9v; higher voltages can be obtained with an external voltage di- vider. high peak current gate drivers provide for fast switch- ing to the external power section, and the output current can be in excess of 20a. the device assures protections against load overcur- rent and overvoltage. an internal crowbar is also pro- vided turning on the low side mosfet as long as the over-voltage is detected. in case of over-current de- tection, the soft start capacitor is discharged and the system works in hiccup mode. so-16 (narrow) htssop16 (exposed pad) ordering numbers: L6910 (so-16) L6910a (htssop16) L6910tr (tape & reel) L6910atr (tape & reel) adjustable step down controller with synchronous rectification block diagram L6910 pgnd phase gnd vfb lgate boot ugate vcc ocset vin 5v to12v vo pgood comp ss monitor protection and ref osc + - + - e/a pwm earef osc vref 300k r t
L6910a L6910 2/21 absolute maximum ratings thermal data (*) device soldered on 1 s2p pc board pins connection (top view) symbol parameter value unit vcc vcc to gnd, pgnd 15 v v boot - v phase boot voltage 15 v v hgate - v phase 15 v ocset, lgate, phase -0.3 to vcc+0.3 v ss, fb, pgood, vref, earef, rt 7 v comp 6.5 v t j junction temperature range -40 to 150 c t stg storage temperature range -40 to 150 c p tot maximum power dissipation at tamb = 25 c1w symbol parameter so-16 htssop16 htssop16 (*) unit r th j-amb thermal resistance junction to ambient 120 110 50 c/w vref osc ocset ss/inh comp gnd fb earef pgood phase boot hgate pgnd lgate vcc n.c. 1 3 2 4 5 6 7 8 14 13 12 11 10 9 15 16 so16 vref osc ocset ss/inh n.c. fb comp gnd earef pgood hgate phase boot pgnd lgate vcc 1 3 2 4 5 6 7 8 14 13 12 11 10 9 15 16 htssop-16
3/21 L6910a L6910 pins function so htssop name description 1 1 vref internal 0.9v 1.5% reference is available for external regulators or for the internal error amplifier (connecting this pin to earef) if external reference is not available. a minimum 1nf capacitor is required. if the pin is forced to a voltage lower than 70%, the device enters the hiccup mode. 2 2 osc oscillator switching frequency pin. connecting an external resistor (r t ) from this pin to gnd, the external frequency is increased according to the equation: connecting a resistor (r t ) from this pin to vcc (12v), the switching frequency is reduced according to the equation: if the pin is not connected, the switching frequency is 200khz. the voltage at this pin is fixed at 1.23v. forcing a 50 m a current into this pin, the built in oscillator stops to switch. in over voltage condition this pin goes over 3v until that conditon is removed. 3 3 ocset a resistor connected from this pin and the upper mos drain sets the current limit protection. the internal 200 m a current generator sinks a constant current through the external resistor. the over-current threshold is due to the following equation: 4 4 ss/inh the soft start time is programmed connecting an external capacitor from this pin and gnd. the internal current generator forces through the capacitor 10 m a. this pin can be used to disable the device forcing a voltage lower than 0.4v 5 6 comp this pin is connected to the error amplifier output and is used to compensate the voltage control feedback loop. 6 7 fb this pin is connected to the error amplifier inverting input and is used to compensate the voltage control feedback loop. connected to the output resistor divider, if used, or directly to vout, it manages also over- voltage conditions and the pgood signal 7 8 gnd all the internal references are referred to this pin. connect it to the pcb signal ground. 8 9 earef error amplifier non-inverting input. connect to this pin an external reference (from 0.9v to 3v) for the pwm regulation or short it to vref pin to use the internal reference. if this pin goes under 650mv (typ), the device shuts down. 910 pgood this pin is an open collector output and it is pulled low if the output voltage is not within the above specified thresholds. if not used it may be left floating. 10 11 phase this pin is connected to the source of the upper mosfet and provides the return path for the high side driver. this pin monitors the drop across the upper mosfet for the current limit together with ocset. 11 12 hgate high side gate driver output. 12 13 boot bootstrap capacitor pin. through this pin is supplied the high side driver and the upper mosfet. connect through a capacitor to the phase pin and through a diode to vcc (cathode vs. boot). 13 14 pgnd power ground pin. this pin has to be connected closely to the low side mosfet source in order to reduce the noise injection into the device 14 5 lgate this pin is the lower mosfet gate driver output 15 16 vcc device supply voltage. the operative supply voltage ranges is from 5v to 12v. do not connect v in to a voltage greater than v cc . 16 5 n.c. this pin is not internally bonded. it may be left floating or connected to gnd. f osc,rt 200khz 4.94 10 6 r t k w () ------------------------- + = f osc,rt 200khz 4.306 10 7 r t k w () ---------------------------- - C = i p i ocset r ocset r dson --------------------------------------------- - =
L6910a L6910 4/21 electrical characteristics (v cc = 12v, t j =25c unless otherwise specified) symbol parameter test condition min typ max unit v cc supply current icc vcc supply current osc = open; ss to gnd 4 7 9 ma power-on turn-on vcc threshold vocset = 4v 4.0 4.3 4.6 v turn-off vcc threshold vocset = 4v 3.8 4.1 4.4 v rising v ocset threshold 1.24 1.4 v turn on earef threshold vocset = 4v 650 750 mv s oft start and inhibit iss soft start current s.s. current in inh condition ss = 2v ss = 0 to 0.4v 610 35 14 60 m a m a oscillator f osc initial accuracy osc = open osc = open; t j = 0 to 125 180 170 200 220 230 khz khz f osc,rt total accuracy 16 k w < r t to gnd < 200 k w -15 15 % d vosc ramp amplitude 1.9 v reference v out output voltage accuracy v out = v fb ; v earef = v ref 0.886 0.900 0.913 v v ref reference voltage c ref = 1nf; i ref = 0 to 100 m a 0.886 0.900 0.913 v v ref reference voltage c ref = 1nf; t j = 0 to 125 c-2 +2% error amplifier i earef n.i. bias current v earef = 3v 10 m a earef input resistance vs. gnd 300 k w i fb i.i. bias current v fb = 0v to 3v 0.01 0.5 m a v cm common mode voltage 0.8 3 v v comp output voltage 0.5 4 v g v open loop voltage gain 70 85 db gbwp gain-bandwidth product 10 mhz sr slew-rate comp = 10pf 10 v/ m s gate drivers i hgate high side source current v boot - v phase = 12v v hgate - v phase = 6v 1 1.3 a r hgate high side sink resistance v boot - v phase = 12v 2 4 w i lgate low side source current vcc = 12v; v lgate = 6v 0.9 1.1 a r lgate low side sink resistance vcc = 12v 1.5 3 w output driver dead time phase connected to gnd 90 210 ns protections i ocset ocset current source v ocset = 4v 170 200 230 m a over voltage trip (v fb / v earef )v fb rising 117 120 % i osc osc sourcing current v fb > ovp trip 15 30 ma power good upper threshold (v fb / v earef )v fb rising 108 110 112 % lower threshold (v fb / v earef )v fb falling 88 90 92 % hysteresis (v fb / v earef ) upper and lower threshold 2 % v pgood pgood voltage low i pgood = -4ma 0.4 v i pgood output leakage current v pgood = 6v 0.2 1 m a
5/21 L6910a L6910 device description the device is an integrated circuit realized in bcd technology. the controller provides complete control logic and protection for a high performance step-down dc-dc converter. it is designed to drive n channel mosfets in a synchronous-rectified buck topology. the output voltage of the converter can be precisely regulated down to 900mv with a maximum tolerance of 1.5% when the internal reference is used (simply connecting together earef and vref pins). the device allows also using an external reference (0.9v to 3v) for the regulation. the device provides voltage-mode control with fast transient response. it includes a 200khz free-running oscillator that is adjustable from 50khz to 1mhz. the error amplifier features a 10mhz gain-bandwidth product and 10v/ m s slew rate that permits to realize high converter bandwidth for fast transient performance. the pwm duty cycle can range from 0% to 100%. the device protects against over-current conditions entering in hiccup mode. the de- vice monitors the current by using the r ds(on) of the upper mosfet(s) that eliminates the need for a current sensing resistor. the device is available in so16 narrow package. oscillator the switching frequency is internally fixed to 200khz. the internal oscillator generates the triangular waveform for the pwm charging and discharging with a constant current an internal capacitor. the current delivered to the oscillator is typically 50 m a (f sw = 200khz) and may be varied using an external resistor (r t ) connected between osc pin and gnd or v cc . since the osc pin is maintained at fixed voltage (typ. 1.235v), the frequency is var- ied proportionally to the current sunk (forced) from (into) the pin. in particular connecting r t vs. gnd the frequency is increased (current is sunk from the pin), according to the following relationship: connecting r t to v cc = 12v or to v cc = 5v the frequency is reduced (current is forced into the pin), according to the following relationships: v cc = 12v v cc = 5v switching frequency variation vs. rt are repeated in fig. 1. note that forcing a 50 m a current into this pin, the device stops switching because no current is delivered to the oscillator. f osc,rt 200kh z 4.94 10 6 r t k w () ------------------------- + = f osc,rt 200kh z 4.306 10 7 r t k w () ---------------------------- - C = f osc,rt 200kh z 15 10 6 r t k w () --------------------- C = figure 1. reference a precise 1.5% 0.9v reference is available. this ref- erence must be filtered with 1nf ceramic capacitor to avoid instability in the internal linear regulator. it is able to deliver up to 100 m a and may be used as ref- erence for the device regulation and also for other de- vices. if forced under 70% of its nominal value, the device enters in hiccup mode until this condition is removed. through the earef pin the reference for the regula- tion is taken. this pin directly connects the non-in- verting input of the error amplifier. an external reference (or the internal 0.9v 1.5%) may be used. the input for this pin can range from 0.9v to 3v. it has an internal pull-down (300k w resistor) that forces the device shutdown if no reference is connected (pin floating). however the device is shut down if the volt- age on the earef pin is lower than 650mv (typ). 10 100 1000 frequency [khz] 10 100 1000 10000 resistance [kohm] rt to gnd rt to vcc=12v rt to vcc=5v
L6910a L6910 6/21 soft start at start-up a ramp is generated charging the external capacitor c ss with an internal current generator. the initial value for this current is of 35 m a and speeds-up the charge of the capacitor up to 0.5v. after that it becames 10 m a until the final charge value of approximatively 4v. when the voltage across the soft start capacitor (v ss ) reaches 0.5v the lower power mos is turned on to dis- charge the output capacitor. as v ss reaches 1.1v (i.e. the oscillator tri angular wave inferior limit) also the upper mos begins to switch and the output voltage starts to increase. no switching activity is observable if ss is kept lower than 0.5v and both mosfets are off. if vcc and ocset pins are not above their own turn-on thresholds and v earef is not above 650mv, the soft- start will not take place, and the relative pin is internally shorted to gnd. during normal operation, if any under- voltage is detected on one of the two supplies, the ss pin is internally shorted to gnd and so the ss capacitor is rapidly discharged. figure 2. soft start (with reference present) driver section the driver capability on the high and low side drivers allows using different types of power mos (also multiple mos to reduce the r dson ), maintaining fast switching transition. the low-side mos driver is supplied directly by vcc while the high-side driver is supplied by the boot pin. adaptative dead time control is implemented to prevent cross-conduction and allow to use several kinds of mos- fets. the upper mos turn-on is avoided if the lower gate is over about 200mv while the lower mos turn-on is avoided if the phase pin is over about 500mv. the lower mos is in any case turned-on after 200ns from the high side turn-off. the peak current is shown for both the upper (fig. 3) and the lower (fig. 4) driver at 5v and 12v. a 3.3nf capac- itive load has been used in these measurements. for the lower driver, the source peak current is 1.1a @ v cc = 12v and 500ma @ v cc = 5v, and the sink peak current is 1.3a @ v cc = 12v and 500ma @ v cc = 5v. similarly, for the upper driver, the source peak current is 1.3a @ vboot-vphase = 12v and 600ma @ vboot- vphase = 5v, and the sink peak current is 1.3a @ vboot-vphase =12v and 550ma @ vboot-vphase = 5v. timing diagram vcc turn-on threshold vin turn-on threshold 0.5v 1v vcc vin vss lgate vout to gnd acquisition: ch1 = phase; ch2 = v out ; ch3 = pgood; ch4 = v ss
7/21 L6910a L6910 figure 3. high side driver peak current. vboot-vphase = 12v (right) vboot-vphase = 5v (left) figure 4. low side driver peak current. v cc = 12v (right) v cc = 5v (left) monitoring and protections the output voltage is monitored by means of pin fb. if it is not within 10% (typ.) of the programmed value, the powergood output is forced low. the device provides overvoltage protection, when the voltage sensed on pin fb reaches a value 17% (typ.) greater than the reference the osc pin is forced high (3v typ.) and the lower driver is turned on as long as the over-voltage is detected. overcurrent protection is performed by the device comparing the drop across the high side mos, due to the r dson , with the voltage across the external resistor (r ocs ) connected between the ocset pin and drain of the upper mos. thus the overcurrent threshold (i p ) can be calculated with the following relationship: where the typical value of i ocs is 200 m a. to calculate the r ocs value it must be considered the maximum r dson (also the variation with temperature) and the minimum value of i ocs . to avoid undesirable trigger of overcurrent protection this relationship must be satisfied: ch1 = high side gate ch4 = gate current ch1 = low side gate ch4 = gate current i p r ocs i ocs r dson --------------------------------- =
L6910a L6910 8/21 where d i is the inductance ripple current and i outmax is the maximum output current. in case of over current detectionthe soft start capacitor is discharged with constant current (10 m a typ.) and when the ss pin reaches 0.5v the soft start phase is restarted. during the soft start the over-current protection is al- ways active and if such kind of event occurs, the device turns off both mosfets, and the ss capacitor is dis- charged again (after reaching the upper threshold of about 4v). the system is now working in hiccup mode, as shown in figure 5. after removing the cause of the over-current, the device restart working normally without power supplies turn off and on. i p i outmax i d 2 ---- - + 3 i peak = figure 5. hiccup mode figure 6. inductor ripple current vs. vout ch1 = ss; ch4 = inductor current 0 1 2 3 4 5 6 7 8 9 0.51.5 2.53.5 output voltage [v] inductor ripple [a] l=3 m h, vin=12v l=2 m h, vin=12v l=1.5 m h , vin=12v l=2 m h, vin=5v l=1.5 m h, vin=5v l=3 m h , vin=5v inductor design the inductance value is defined by a compromise between the transient response time, the efficiency, the cost and the size. the inductor has to be calculated to sustain the output and the input voltage variation to maintain the ripple current d i l between 20% and 30% of the maximum output current. the inductance value can be cal- culated with this relationship: where f sw is the switching frequency, v in is the input voltage and v out is the output voltage. figure 6 shows the ripple current vs. the output voltage for different values of the inductor, with v in = 5v and v in = 12v. increasing the value of the inductance reduces the ripple current but, at the same time, reduces the converter response time to a load transient. if the compensation network is well designed, the device is able to open or close the duty cycle up to 100% or down to 0%. the response time is now the time required by the inductor to change its current from initial to final value. since the inductor has not finished its charging time, the output cur- rent is supplied by the output capacitors. minimizing the response time can minimize the output capacitance required. the response time to a load transient is different for the application or the removal of the load: if during the ap- plication of the load the inductor is charged by a voltage equal to the difference between the input and the output voltage, during the removal it is discharged only by the output voltage. the following expressions give approx- imate response time for d i load transient in case of enough fast compensation network response: the worst condition depends on the input voltage available and the output voltage selected. anyway the worst case is the response time after removal of the load with the minimum output voltage programmed and the max- imum input voltage available. l v in v out C f sw i l d ------------------------------ v out v in -------------- - = t application li d v in v out C ------------------------------ t removal li d v out -------------- - ==
9/21 L6910a L6910 output capacitor the output capacitor is a basic component for the fast response of the power supply. in fact, during load tran- sient, for first few microseconds they supply the current to the load. the controller recognizes immediately the load transient and sets the duty cycle at 100%, but the current slope is limited by the inductor value. the output voltage has a first drop due to the current variation inside the capacitor (neglecting the effect of the esl): a minimum capacitor value is required to sustain the current during the load transient without discharge it. the voltage drop due to the output capacitor discharge is given by the following equation: where d max is the maximum duty cycle value that is 100%. the lower is the esr, the lower is the output drop during load transient and the lower is the output voltage static ripple. input capacitor the input capacitor has to sustain the ripple current produced during the on time of the upper mos, so it must have a low esr to minimize the losses. the rms value of this ripple is: where d is the duty cycle. the equation reaches its maximum value with d = 0.5. the losses in worst case are: compensation network design the control loop is a voltage mode (figure 7). the output voltage is regulated to the input reference voltage level (earef). the error amplifier output v comp is then compared with the osc illator tri angular wave to provide a pulse-width modulated (pwm) wave with an amplitude of v in at the phase node. this wave is filtered by the output filter. the modulator transfer function is the small-signal transfer function of v out /v comp . this function has a double pole at frequency f lc depending on the l-c out resonance and a zero at f esr depending on the output capacitor esr. the dc gain of the modulator is simply the input voltage v in divided by the peak-to-peak oscillator voltage d v osc . v out d i out d esr = v out d i out 2 d l 2c out v inmin d max v out C () --------------------------------------------------------------------------------------------- = i rms i out d1d C () = p esr i rms 2 =
L6910a L6910 10/21 figure 7. compensation network the compensation network consists in the internal error amplifier and the impedance networks z in (r3, r4 and c20) and z fb (r5, c18 and c19). the compensation network has to provide a closed loop transfer function with the highest 0db crossing frequency to have fast response (but always lower than fsw/10) and the highest gain in dc conditions to minimize the load regulation. a stable control loop has a gain crossing with -20db/decade slope and a phase margin greater than 45. include worst-case component variations when determining phase margin. to locate poles and zeroes of the compensation networks, the following suggestions may be used: modulator singularity frequencies: compensation network singularity frequency: C put the gain r5/r3 in order to obtain the desired converter bandwidth; Cplace w z1 before the output filter resonance w lc ; Cplace w z2 at the output filter resonance w lc ; Cplace w p1 at the output capacitor esr zero w esr ; Cplace w p2 at one half of the switching frequency; C check the loop gain considering the error amplifier open loop gain. vin l esr cout r3 r5 c19 earef vcomp pwm comparator vout d vosc r4 c18 c20 + - w lc 1 lc out --------------------------- w esr 1 esr c out -------------------------------- - == w p1 1 r5 c18 c19 c18 c19 + ---------------------------- - ?? ?? ----------------------------------------------- w p2 1 r4 c20 ----------------------- - == w z1 1 r5 c19 ----------------------- - w z2 1 r3 r4 + () c20 ------------------------------------------- ==
11/21 L6910a L6910 figure 8. asymptotic bode plot of converter's gain 20a demo board description the demo board shows the operation of the device in a general purpose application. this evaluation board al- lows voltage adjustability from 0.9v to 5v through the switches s2-s5 according to the reported table when the internal 0.9v reference is used (g1 closed). output current in excess of 20a can be reached dependently on the kind of mosfet used: up to three so8 mosfet may be used for both high side and low side switches. external reference may be used for the regulation simply leaving open g1 and the switches s2-s5. the device may also be disabled with the switch s1. the 12v input rail supplies the device while the power conversion starts from the 5v input rail. the device is also able to operate with a single supply voltage; in this case the jumper g2 has to be closed and a 5v to 12v input can be directly connected to the v in input. the four layers demo board's copper thickness is of 70 m m in order to minimize conduction losses considering the high current that the circuit is able to deliver. figure 9 shows the demo board's schematic circuit figure 9. 20a demo board schematic error amplifier w z1 w z2 w p1 w p2 w esr r5/r3 modulator gain compensation network gain error amplifier closed loop gain w lc w db l2 l1 r7 c1 -c3 c14 c4 -11 q4 -6 q1 -3 d2 c17 f1 13 14 10 11 3 1 u1 L6910 vin vout pwrgd 6 12 5 4 2 15 7 9 vcc gnd vref ss osc ocset ugate phase lgate pgnd pgo od vfb com p c19 r1 c21 c13 d1 gndin gndou t r2 gndref +vref c12 gndref in ref in c16 g1 c15 r6 c18 8 gndcc vcc r5 g2 r3 r4 c20 s1 s2 s3 s4 s5 r10 r11 r12 r13 earef boot vout s2 s3 s4 s5 0.9 1.2 1.5 1.8 2.5 3.3 5.0 open open on ope n open open open open open open open open open open open open open on on on open open on on on on open open
L6910a L6910 12/21 figure 10. pcb and components layouts figure 11. pcb and components layouts figures 10 and 11 show the demo board layout. considering the flexibility in the power mosfet configuration (up to three mosfet for both high side and low side), it is possible to obtain different application idea with the same board. in the following paragraphs, it will be described the standard demo-board configuration (8a) and the high current configuration. application idea: 5v to 12v input; 0.9v to 5v / 8a output this is a typical bus termination application in which the output voltage is programmed by the switch to 1.2v typ (it can range from 0.9v to 5v) and the maximum output current is of 8a dc. the power mosfet are configured with one sts12nf30l (30v, 10m w typ @ vgs=4.5v ) for both hgih side and low side. inductor selection since the maximum output current is 8a, to have a 15% ripple (1a) in worst case the inductor chosen is 4.1 m h. sumida cee125 series inductor has been chosen with a 4.2 m a typical value. component side internal signal gnd layer internal power gnd layer solder side
13/21 L6910a L6910 output capacitor in the demo 5 poscap capacitors, model 6tpb330m, are used, with a maximum esr equal to 40m w each. therefore the resultant esr is of 8m w . for load transient of 8a in the worst case the voltage drop is of: d v out = 8 0.008 = 64mv the voltage drop due to the capacitor discharge during load transient, considering that the maximum duty cycle is equal to 100% results in 16.4mv with 1.2v of programmed output. input capacitor for i out = 8a and d=0.5 (worst case for input ripple current), irms is equal to 4a. three oscon electrolytic capacitors 20sa100m, with a maximum esr equal to 30m w , are chosen to sustain the ripple. therefore, the resultant esr is equal to 30m w /3 = 10m w . so the losses in worst case are: p = esr = 160mw over-current protection the peak current is in this case equal to 12a, substituting the demo board parameters in the relationship report- ed in the relative section, (i ocsmin = 170 m a; i p = 12a; r dsonmax = 9m w ) it results that r ocs = 620 w . efficiency figure 12 shows the measured efficiency versus load current for different values of output voltage. the measure was done at v in = 5v for different values of the output voltage (0.9v, 1.2v, 1.5v, 1.8v, 2.5v and 3.3v). ic supply voltage is of 12v. in the application one mosfets sts12nf30l (30v, 10m w typ @ v gs = 4.5v) is used for both the low and the high side. since the board has been layed out with the possibility to use up to three so8 mosfets for both high and low side switch, to increase efficiency at low output voltages, an additional mosfet on the low side can be considered because of the duty cycle. table 1. part list r2 10k smd 0805 r3 4.7k 1% smd 0805 r5 47k smd 0805 r6 10 smd 0805 r7 620 smd 0805 r10 14k e96 1% smd 0805 r11 6.98k e96 1% (optional) smd 0805 r12 2.61k e96 1% (optional) smd 0805 r13 1.74k e96 1% (optional) smd 0805 c1 100 m oscon - 20sa100m radial 10x10.5mm c4c11 330 m poscap - 6tpb330m smd 7343 c12, c13, c15, c21 100n ceramic smd 0805 c14 1n ceramic smd 0805 c19 56n ceramic smd 0805 l1 1.5 m t44-52 core, 7t-18awg l2 4.2 m sumida cee125 series u1 L6910 stmicroelectronics so16 narrow q1, q4 sts12nf30l stmicroelectronics so8 d1 1n4148 stmicroelectronics sot23 d2 stps3340u stmicroelectronics smb f1 251015a-15 littlefuse axial i rms 2
L6910a L6910 14/21 figure 12. demo board efficiency @ v in = 5v application idea: 5v to 12v input; 3.3v / 25a output this is a typical application to replace the mag-amp in the silver box. the output voltage is programmed by the switch to 3.3v and the maximum output current is of 25a dc. the power mosfet are configured with three sts11nf30l (30v, 9m w typ @ v gs = 10v ) for high side and two of them for the low side. inductor selection since the maximum output current is 25a, to have a 20% ripple (5a) in worst case the inductor chosen is 1.1 m h. an iron powder core (to50-52b) with 6 windings has been chosen. output capacitor 4 poscap capacitors, model 6tpb330m, are used, with a maximum esr equal to 40m w each. therefore the resultant esr is of 10m w . for load transient of 20a in the worst case the voltage drop is lower than 5%: d v out = 20 0.01 = 200mv input capacitor for i out = 25a and d = 0.5 (worst case for input ripple current), irms is equal to 12.5a. three oscon electro- lytic capacitors 6sp680m, with a maximum esr equal to 13m w , are chosen to sustain the ripple. therefore, the resultant esr is equal to 13m w /3 = 4.3m w . so the losses in worst case are: p = esr = 670mw over-current protection the peak current is in this case equal to 30a, substituting the demo board parameters in the relationship report- ed in the relative section, (i ocsmin = 170 m a; i p = 30a; r dsonmax = 3m w ) it results that r ocs = 530 w . 60 65 70 75 80 85 90 95 0246810 output current [a] efficiency [%] vout = 0.9v vout = 1.2v vout = 1.5v vout = 1.8v vout = 2.5v vout = 3.3v i rms 2
15/21 L6910a L6910 efficiency figure 13 shows the measured efficiency versus load current at vin=5v. in the application three mosfets sts11nf30l (30v, 9m w typ @ v gs = 10v) are used for high side swith while two of them are used for the low side.. figure 13. demo board efficiency @ v in = 5v & v out = 3.3v table 2. part list r2 10k smd 0805 r3 4.7k 1% smd 0805 r4 220 smd 0805 r5 10k smd 0805 r6 10 smd 0805 r7 620 smd 0805 r9 0 smd 0805 r10 1.74k 1% smd 0805 c1,c2, c3 680 m oscon - 6sp680m radial 10x10.5mm c4 to c8 330 m poscap - 6tpb330m smd 7343 c13, c15 100n ceramic smd 0805 c14, c16 1n ceramic smd 0805 c18 2.2n ceramic smd 0805 c19 3.3n ceramic smd 0805 c20 6.8n ceramic smd 0805 l1 1.5 m t44-52 core, 7t-18awg l2 1.1 m t50-52b core, 6t u1 L6910 stmicroelectronics so16 narrow q1 to q5 sts11nf30l stmicroelectronics so8 d1 1n4148 stmicroelectronics sot23 d2 stps340u stmicroelectronics smb f1 251015a-15 littlefuse axial 85 87 89 91 93 95 97 0 5 10 15 20 25 output current efficiency
L6910a L6910 16/21 5a demo board description the demo board shows the operation of the device in a general purpose application. the interanl reference is used for the regulation. the external power mosfets are included in one so8 package to save space and in- crease power density.the 12v input rail supplies the device while the power conversion starts from the 5v input rail. the device is also able to operate with a single supply voltage; in this case the jumper j1on the board bot- tom has to be closed and a 5v to 12v input can be directly connected to the v in input. figure 14. 5a demo board schematic figure 15. pcb and components layouts efficiency figure 16 shows the measured efficiency versus load current for different values of output voltage. the measure was done at 5v and 12v input for different values of the output voltage (2.5v, 3.3v and 5v only when vin=12v). output voltage has been changed modifying the value of r1 in the demo board as reported in the part list. l1 r7 c1,c2 c7 c3, c4 q1/2 q1/1 13 14 10 11 3 1 u1 L6910 vin (+5v) vout pwrgd 6 12 5 4 2 15 7 9 vcc gnd vref ss osc ocset ugate phase lgate pgnd pgood vfb comp c19 r1 c9 c6 d1 gndin gndou t r2 c8 c5 r6 c18 8 r5 r3 r4 c20 earef boot r9 r8 r10 d2 c10 r11 gndcc j1 vcc (+12v) component side solder side
17/21 L6910a L6910 figure 16. demoboard efficiency with v cc = v in = 5v (left), and with v cc = v in = 12v (right). part list resistors r1 560 375 220 1%; (vout = 2.5v) 1%; (vout = 3.3v) 1%; (vout = 5v) smd 0805 r2 10k smd 0805 r3 1k smd 0805 r4 33 smd 0805 r5 2.7k smd 0805 r6 10 smd 0805 r7 680 smd 0805 r8, r9 2.2 smd 0805 capacitors c1,c2 10 m f tokin c34y5u1e106zte12 smd 7343 c3, c4 100 m f C 6.3v poscap 6tpb100m smd 7343 c5,c6,c9 100nf smd 0805 c7, c8 1nf smd 0805 c18 1.5n smd 0805 c19 15n smd 0805 c20 47n smd 0805 magnetics l1 10h t50-52b core, 12t transistors q1 sts7dnf30l stmicroelectronics so8 diodes d1 1n4148 sot23 d2 stps125a stmicroelectronics sma ics u1 L6910 stmicroelectronics so16narrow 85 86 87 88 89 90 91 92 93 94 95 012345 output current [a] efficiency [%] vout=3.3v vout=2.5v 60 65 70 75 80 85 90 95 012345 output current [a] efficiency [%] vout=2.5v vout=3.3v vout=5v
L6910a L6910 18/21 application idea: buck-boost converter 3v to 10v input / 5v 2a output figure 17. buck-boost converter 3v to 10v input / 5v 2a output circuit l1 r7 c1,c2 c7 c3, c4 q1/2 q1/1 13 14 10 11 3 1 u1 L6910 vin (+2.5v to +12v) vout pwrgd 6 12 5 4 2 15 7 9 vcc gnd vref ss osc ocset ugate phase lgate pgnd pgood vfb comp c19 r1 c9 c6 d1 gndin gndout r2 c8 c5 r6 c18 8 r5 r3 r4 c20 earef boot r9 r8 r10 d2 gndcc vcc (+12v) q2/1 q2/2 d3
19/21 L6910a L6910 so16 narrow dim. mm inch min. typ. max. min. typ. max. a 1.75 0.069 a1 0.1 0.25 0.004 0.009 a2 1.6 0.063 b 0.35 0.46 0.014 0.018 b1 0.19 0.25 0.007 0.010 c 0.5 0.020 c1 45? (typ.) d (1) 9.8 10 0.386 0.394 e 5.8 6.2 0.228 0.244 e 1.27 0.050 e3 8.89 0.350 f (1) 3.8 4 0.150 0.157 g 4.6 5.3 0.181 0.209 l 0.4 1.27 0.016 0.050 m 0.62 0.024 s (1) d and f do not include mold flash or protrusions. mold flash or potrusions shall not exceed 0.15mm (.006inch). outline and mechanical data 8?(max.) 0016020 weight: 0.20gr
L6910a L6910 20/21 outline and mechanical data dim. mm inch min. typ. max. min. typ. max. a 1.2 0.047 a1 0.15 0.006 a2 0.8 1.0 1.05 0.031 0.039 0.041 b 0.19 0.3 0.007 0.012 c 0.09 0.2 0.003 0.008 d (*) 4.9 5.0 5.1 0.192 0.197 0.200 d1 1.7 0.067 e 6.2 6.4 6.6 0.244 0.252 0.260 e1 (*) 4.3 4.4 4.5 0.169 0.173 0.177 e2 1.5 0.059 e 0.65 0.026 l 0.45 0.6 0.75 0.018 0.024 0.029 l1 1.0 0.039 k 0? (min), 8? (max) aaa 0.10 0.004 (*) dimensions d and e1 does not include mold flash or protusions. mold flash or protusions shall not exeed 0.15mm per side. htssop16 7419276 (exposed pad) 3.0 3.0 0.118 0.118
information furnished is believed to be accurate and reliable. however, stmicroelectronics assumes no responsibility for the co nsequences of use of such information nor for any infringement of patents or other rights of third parties which may result from its use. no license is granted by implication or otherwise under any patent or patent rights of stmicroelectronics. specifications mentioned in this publicati on are subject to change without notice. this publication supersedes and replaces all information previously supplied. stmicroelectronics prod ucts are not authorized for use as critical components in life support devices or systems without express written approval of stmicroelectro nics. the st logo is a registered trademark of stmicroelectronics ? 2003 stmicroelectronics - all rights reserved stmicroelectronics group of companies australia - brazil - canada - china - finland - france - germany - hong kong - india - israel - italy - japan -malaysia - malta - morocco - singapore - spain - sweden - switzerland - united kingdom - united states. http://www.st.com 21/21 L6910a L6910

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